Technical Field of the Disclosure
This disclosure relates in general to integrated circuit design and testing, and in particular to a circuit test architecture that enables low power testing of embedded circuit core functions using a simplified tester interface.
A System On a Chip (SOC) design may consist of many types of embedded core functions such as DSPs, CPUs, memories, and various other types. Typically the testing of embedded cores is achieved by scan testing the cores. Conventional core scan testing is achieved by placing the core in a test mode whereby scan inputs to the core and scan outputs from the core are made available for access by a tester external to the SOC.
While there are many publications on scan testing, a paper by Marinissen (Scan Chain Design for Test Time Reduction in Core Based ICs”, 1998 IEEE International Test Conference) is chosen to provide background information on conventional methods of scan testing cores in an SOC. This paper describes the following three types of core scan test configurations that can be used in an SOC.
The first core scan test configuration described in regard to FIG. 1 of the paper is referred to as a multiplexing architecture. In the multiplexing architecture, the scan inputs of multiple cores are connected to a common scan input bus from a tester while the scan outputs of the multiple cores are individually multiplexed to a common scan out bus to the tester. During test, the tester individually selects one core at a time and tests the core using the scan input and scan output bus. The test is complete after all cores have been individually selected and tested.
The second core scan test configuration described in regard to FIG. 2 of the paper is referred to as a daisychain architecture. In the daisychain architecture, the scan inputs and outputs of multiple individual cores are serially connected to form a daisychained scan path from the tester's scan input to the tester's scan output. During test, the tester accesses the daisychained core scan paths and applies the scan test to the cores. The test is complete after all cores on the daisychain scan path have been tested.
The third core scan test configuration described in regard to FIG. 3 of the paper is referred to as a distribution architecture. In the distribution architecture, the scan inputs and outputs of each core are made individually accessible by a tester. This means that the tester needs to have a scan input and scan output bus dedicated for testing each core. During test, the tester accesses each core's scan input and scan output buses and tests each core in parallel. The test is complete after all cores in the distribution architecture have been tested.
From the above description it is clear that each of the scan test configurations require the tester to receive, either directly as in the multiplexing and distribution architectures or indirectly as in the daisychain architecture, the scan outputs from each core being tested. Having to include circuitry in testers for receiving scan output data from an SOC increases the cost of the tester and leads to larger test access interfaces between the tester and SOC. It should also be clear that the power consumed and heat generated during parallel core testing using the distribution and daisychain configurations may limit the number of cores that may be tested in parallel and force the testing to occur sequentially over a number of smaller core groups. Having to partition a plurality of cores to be tested into small separately tested groups to manage SOC power consumption and heat generation leads to longer test times and increases the cost of the SOC.